1. Field of the Invention
The present invention generally relates to dynamic random access memories and, more particularly, is directed to a dynamic random access memory in which a stacked capacitor for charge accumulation is connected to a switching element.
2. Description of the Prior Art
Recently, a stacked capacitor cell having a capacitor of a stacked type structure for storing informations has been utilized in order to keep a capacitance as semiconductor memories such as a dynamic random access memory (DRAM) or the like are highly integrated. This type of semiconductor memory is reported in international electron devices meeting held on Dec. 11, 1988, pp.596-599.
As shown in FIG. 1, in a conventional semiconductor memory having a stacked capacitor, an impurity diffusion layer 33 of a switching element Tr is formed to face the surface of a silicon substrate 32 on which a field insulating layer 31 is formed. One source-drain region 33a of the impurity diffusion region 33 is connected with a bit line 35 formed, for example, of an Al wiring layer through a contact hole 34, and the other source-drain region 33b is connected with a capacitor lower portion electrode 36 of a stacked capacitor C.
The capacitor lower portion electrode 36 is formed by the patterning-process of a polycrystalline silicon layer of the second layer. This capacitor lower portion electrode 36 is formed up to the upper portion of each gate electrode 37 of the switching element Tr which is a polycrystalline silicon layer of the first layer through an interlevel insulator 38. The capacitor lower portion electrode 36 has on its upper portion formed a capacitor upper portion electrode 39 as a common electrode through a dielectric layer 40, and a multilayer structure of these capacitor upper electrode 39, dielectric layer 40 and capacitor lower portion electrode 36 constructs the stacked capacitor C.
In this semiconductor memory device, necessary charges and so on are accumulated in the stacked capacitor C and the write and read therein and therefrom are carried out by means of the bit line 35 under the control of the switching element Tr.
However, since the conventional semiconductor memory device has the multilayer structure in which several polycrystalline silicon layer are stacked on the silicon substrate 32, a step at the contact portion in the memory cell portion is increased so that a step coverage in the contact hole or the like is deteriorated. There is then the disadvantage that the patterning-process on the upper layer, e.g., the patterning-process such as the bit line 35 or the like becomes difficult. Further, in order to increase the capacitance of the stacked capacitor C so as to cope with highly integrated semiconductor memories, a side wall of the capacitor lower portion electrode 36 which becomes an accumulation node must be effectively utilized. If so, then the step of the capacitor lower portion electrode 36 is increased. Accordingly, the step at the above-mentioned contact portion is increased, thus giving rise to the disconnection of the bit line 35 or the like.
Furthermore, if the step at the memory cell portion is increased, then the patterning-process of the wiring or the like becomes difficult in the connected portion with the peripheral circuit portion (e.g., address decoder or the like) where the step is relatively small due to a difference of depth of focus during the exposure.